This invention relates generally to a semiconductor integrated circuit (SIC) device and in particular, to an SIC device capable of performing "on-wafer" circuit testing or burn-in on a great number of SICs formed on a single wafer.
A high-speed, high-performance SIC capable of rapidly processing a great amount of information is considered a multimedia key device. Generally, in order to have a plurality of SIC devices operate at the same timing their operations are synchronized with one another by a high-speed clock signal (i.e., a clock signal of from tens of megahertz to hundreds of megahertz).
As the level of SIC integration increases, and as the functionality of SIC increases, testing SIC devices becomes complicated and hence testing costs increase.
Additionally, it becomes necessary to identify early failures by means of a burn-in procedure, and the length of burn-in time increases.
In order to reduce the costs of testing, Japanese Patent Applications, laid open without substantial examination thereof under Nos. 03-216899 and 03-216900, show techniques. That is, a self-test circuit is incorporated into an SIC device, and is assigned a task to conduct a part of the SIC testing.
On the other hand, Japanese Patent Application, laid open without substantial examination thereof under No. 04-139850, shows a technique. This technique uses self-test circuits incorporated into SIC devices for on-wafer circuit testing or burn-in, and all the SIC devices are simultaneously subjected to a burn-in procedure with less contact.
In order to simultaneously subject a great number of SICs, which are formed on the same wafer and which operate in synchronism with an external signal, to an on-wafer circuit testing process or to a burn-in process by built-in self-test circuits, high-speed synchronizing signals must be applied to all the SIC devices in which the self-test circuit are incorporated. It is however difficult to transmit, in a multidrop fashion, high-speed synchronizing signals to many SIC devices (e.g., 100 SIC devices) formed on, for example, a wafer having a diameter of 20 cm because of external environments (e.g., noise).
Although it is possible to generate high-speed synchronizing signals within an SIC device, it is hard to generate high-accuracy synchronizing signals because of manufacturing processing instability. Therefore, a conventional technique employing an approach of generating high-speed synchronizing signals within an SIC device may suffer poor testing accuracy.
Transmission of high-speed, high-accuracy synchronizing signals to individual SICs formed on the same wafer is impossible (the first problem).
Additionally, a conventional self-test circuit functions, only to determine whether the quality of SICs is satisfactory. For the case of some recent generations of semiconductor memories, even if it is found that some memory elements fail to work properly, these unsatisfactory elements are able to be remedied by a post-testing redundant remedy step. In other words, in a method of conducting on-wafer circuit testing with the aid of a self-test circuit, or a burn-in before a redundant remedy step, even a semiconductor memory that has a possibility of being remedied at a later step is classified as an unsatisfactory semiconductor memory.
The employment of built-in self-test circuits cannot make it possible to determine whether a SIC device is satisfactory before a redundant remedy step. Burn-in time is wasted (the second problem).
Voltages are applied to individual SICs via a common power supply line at the time of conducting on-wafer circuit testing or burn-in, and the SICs are connected in parallel with the common power supply line. Generally, a current flowing through a power supply line is greater than a current flowing through a signal line, therefore suffering a drop in voltage because of its own resistance. As a result, different voltages are applied to individual SIC devices according to their locations on a wafer (the third problem).
There is a possibility that some of many SIC devices are unsatisfactory ones. If such failure is caused by, for example, short circuiting between an SIC device's power source and ground, an excess current flows in an unsatisfactory SIC device thereby affecting the way in which the other SIC devices are burned-in. Even if an unsatisfactory SIC device is removed by, for example, cutting a power supply line before a burn-in step, there is still a possibility that a different SIC device becomes an unsatisfactory one during the burn-in step.
As described above, the presence of an unsatisfactory SIC device prevents accurate testing or burn-in (the fourth problem).